Quoting from https://fuse.wikichip.org/news/2879/tsmc-5-nanometer-update/
“TSMC also disclosed its 5-nanometer 6T SRAM bitcell. The high-density N5 6T cell is 0.021µm², making it the densest production cell reported to date. Assuming a ballpark assist circuit overhead of around 30%, this works out to ~32 Mib/mm² of cache.”
That suggests a future Cuckatoo32 ASIC featuring 1GB of SRAM could be 256mm² in size. Or perhaps using 512MB SRAM and 512MB external HBM will offer better economics.
Initial C31+ ASICs are expected to use a much more affordable 10-16nm process though, and 7nm chips could still be several years off at Grin’s current price…
That’s a breakthrough, curious where that silicon limit is. 2 nanometer is expected around 2024. Looking forward to more energy efficient ASICs, perhaps one day they can be passively cooled (silent+fanless) as seen with my desktop build: http://www.neo-geo.com/personal/i5-fanless/build2/finished.jpg
I do like c29/c31 for GPU mining. Memory intensive instead of core means less heat, lower energy bill, less wear to hardware. Had very few RMAs this year, thanks to mining Grin.
With IEDM 2019 around the corner, one can expect more news releases coming out from the foundries or silicon process technology leaders.
WRT to this 5nm article, it may have been pushed out to draw the spot light away from the recent Samsung Tech Day.
Or perhaps to deflate any positive news from Intel’s recent quarterly announcement.
…all about capturing the eye-balls of the readers and mind share of the reporters.
The difference with an industry that is more mature (like silicon tech), the info that is released, is fact-based. These multi-nationals have a code of conduct and their reputations to uphold.
Quite the contrast to some of the miners…very little integrity, …“catch me if you can and keep sending us your money”. It is a terrible motto to operate under. Others can disagree but the complete silence & absence of response is telling.
Well let’s keep silicon in the US then!