SRAM hasn’t changed much in several decades, so I guess several decades more.
There were no expectations, only hopes. There was controversy about the hardware becoming obsolete and the uncertainty of ASIC availability. This was dealt with by no longer obsoleting graph sizes from C32 onwards.
Each core would need to be able to access the entire SRAM, and to do so at the individual bit level. The latter aspect would need to be designed in, or could be emulated with atomic bitset instructions at the word level, but presumably at some loss in efficiency.
Perhaps there are other applications dominated by random access to large data sets; although normally programmers try to work around them to make programs “cache friendly”.
You mean by brute force enumeration of all possible 42-subsets of edges? (2^32 choose 42) = 273297632825084404598054484868481024425629982655167111117619656626245913112251997500993075175804346891407198618675974136225096725318235540049122409884614993703965568742315043925090075293838962101483013522920868615181281701190851860834002052890129275779043084264832079870442459862838280094824993256326451886540385118808639658200791330142256228306213928960