GRIN asic manufacturer parental firm Nano Labs is being listed at Nasdaq-USA exchange.
There is an official listing document, and some interesting INFO about GRIN. There are some metrics and ideas.
I wanted to share it with community.
GRIN first G1 asic machines gives Nano LABS a competitve strength because of first mover advantage, GRIN asic market.
They are proud of Cuckoo chips- super energy efficiency for GRIN home mining, and there coming more Cuckoo chips. Energy efficiency for home mining is crucial for decentralization of network. Imagine every house has a G1 Mini . Maybe @tromp can enlighten us about that.
Bitcoin, Ethereum, GRIN.
Your brand name is mentioned between top 2 cryptocurrency for a listing formal process at the worlds biggest tech exchange Nasdaq! .Every top dog will know or search now what is ‘‘GRIN’’
Ipollo should be credited for making home mining affordable, with prices well below $1K and currently even below $300.
But, to also make home mining more attractive, there is much work to be done on noise levels.
That reminds me of that Hofstadter book: Gödel, Escher, Bach: an Eternal Golden Braid
The section on architecture is of particular interest:
Our Nano FPU Architecture
The development of emerging technologies such as cloud computing, blockchain, artificial intelligence and big data is expected to drive the computing industry into an epoch, which, we believe, not only requires improved computing power and memory performance but also data flow efficiency. The Nano FPU architecture embodies our vision of the future trend of high throughput computing and high-performance computing. The Nano FPU architecture is designed for maintaining the reusability and iterability of IP cores and adapting to the fast-evolving market demand for high performance computing.
The following graphic sets forth an illustration of the Nano FPU architecture:
The Nano FPU architecture primarily consists of four types of basic modules, i.e., Smart-NOC, HBM 3D controller, FPU core and ulPower DVS. Unlike traditional CPU and GPU architectures, our Nano FPU architecture aims to optimize data flow and increase energy consumption efficiency. Smart-NOC enables cache memory to be shared in multicore processing units, which increases the efficiency of data exchange between CPU and memory. HBM 3D controller is designed to increase the data transmission efficiency between DRAM and CPU, and our self-defined high bandwidth memory has a bandwidth ten times as much as traditional HBM 2.0 (4-Hi). FPU core is the processing core for data stream optimization that is upgradable locally or as a whole in a multi-core system to meet different computing needs. Finally, ulPower DVS applies our proprietary dynamic voltage scaling technology, which significantly optimizes the PPA of our chips and lower the total cost of ownership of our products. These IP cores are both separately upgradable and compatible with each other in terms of integration, allowing for great flexibility in application for the Nano FPU architecture.
We have successfully developed Cuckoo 1.0 and Cuckoo 2.0 chips
built on our Nano-FPU architecture and achieved fast iteration from Nano FPU 1.0 to Nano FPU 2.0 within only approximately eight months. We are in the process of designing Nano FPU 3.0, which is expected to be the architecture for the next generation of our Cuckoo series.
I wish there were more details on amounts of SRAM in the different Cuckoo chips. Presumably this is part of the Smart-NOC (Network On Chip), and is suspected at 64MB (2^29 Mbit) in Cuckoo1, which supports lean mining with 2^32/2^29=8 passes for each trimming round. Each doubling of on-chip SRAM would double the efficiency, up to the 512MB that allows single pass trimming. Fitting that much SRAM on a chip requires a 7nm process however, requiring MUCH higher development costs.
@tromp The elliptical geometry discussed in Eternal Golden braid, is that the basis of elliptic curve cryptography? Or is that not the part you are referring to as the interesting section on architecture?