Before further discussion, I want to emphasize again that for official information please refer to our website: http://www.innosilicon.com/html/grin-miner/index.html
Now back to the topic around GPS & memory architecture. First of all, even though DRAM needs to be refreshed every few milliseconds, when using at full speed it is typically less than 10% of the total power consumption. Most of the energy is spent moving data from point A to point B. Let’s examine access energy of two popular high speed DRAMs: GDDR and HBM.
HBM is a few times more efficient than GDDR because it is connected to the Core ASIC through an interposer. The energy to access a bit in HBM2 is about 4pJ/bit, most of that is data movement both on the DRAM die and from the base layer die to reach the I/O pins. To visualize this let’s look at a picture showing how data travels:
Currently HBM is still too expensive for mining ASICs. On the other hand, TSMC has announced the availability of Wafer-on-Wafer (WOW) technology which allows you to stack two logic dies and connect them through TSV. This is a cheaper alternative than using HBM. Also because there is no interposer it allows higher bandwidth. This opens the possibility of building an SRAM chip and stack it with your ASIC core.
In order to design an energy efficient ASIC for GRIN, one has the task of minimizing data movement. I will make a few observations here. It is not meant to disclose our particular method but will stimulate thinking. For example, if you goes with single chip ASIC, you can’t treat 512MiB of SRAM like one big memory chunk. The SRAM size on 16nm will be over 22mm on each side. A completely random access of this SRAM block is not efficient. This is an area where AI technology overlaps with GRIN Mining. Ideas like processing in memory (PIM) has to be considered where logic is mixed with SRAM to minimize power consumption and increase speed. Again, instead of focusing on building high bandwidth, you should at the same time think about minimizing movement. This is true both for both single and multiple chip design.