Scheduled PoW upgrades proposal

There are other memory types apart from 6T SRAM. Nobody is forcing SRAM lean mining. Seems much more interesting compared to monolithic 7nm (stealth) single cuckatoo32 chips.

While it likely won’t be morres law type growth, there are other options to increase “transistor” efficiency.

If its a “reversible gate”, current isn’t being intentionally sent to ground, so that election is still in the circuit for a bit longer. Or something like that.

I think the linear assumption is fine, the transistor “brick wall” has smart people working on it.

Not assuming that either. Only assuming that, whereas memory capacities have historically grown exponentially, they will keep growing at least linearly in the future.

@photon are there 7nm cuckatoo32 chips already? If yes, who is making them?

Not that we know of. Seems unlikely since cuckatoo didn’t even exist up until a couple of weeks ago.

This proposal was adopted as is in the latest Governance meeting.

Sorry to resurrect an old thread, but why is it desirable to avoid single-chip ASICs?

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So that the miners more resemble general purpose computing hardware with separate memory chips, with the potential to accelerate advances in memory technology and adoption thereof. Obsolete mining hardware with lots of fast memory chips also offers more hope of recyclability.

I’m concerned that such advances in memory technology would almost certainly be patentable. This would allow the firm that developed and patented these advances to monopolize mining, and thus reduce or destroy competition between manufacturers.

I think that instead of a boon, it could be a disaster. Edit: Similar to Asicboost, for example.

Recyclability is certainly desirable, but I think that ensuring a competitive mining landscape is more important.

Also, technologies like EMIB[0] might reduce the penalty for inter-die communication in multi-die chip designs, making multi-die designs have similar bandwidth/latency when compared to single-die designs.

[0] https://www.intel.com/content/www/us/en/foundry/emib.html

It’s possible, but we’ve seen groups like NVIDIA who own patents selling their products instead of using them to mine themselves. Unlike asic designs, memory designs are marketable to a wider audience. the greater greed may not have anythign to do with mining.

Also, sorry for not phrasing the initial question like this, but what would the benefits to Grin itself be? Advancing in memory technology and promoting recycling are worthy goals, but I think that the proof of work should be chosen primarily based on its merits with respect to the health of the system.

In that sense it’s a big experiment, to see if memory IO bound PoW can yield as competitive a mining competition as compute bound IO does. Which may take many years to find out.

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grin will launch with 10% ramp to 90% so

cuckatoo32 is for 10% to 55%
cuckatoo33 is for 55% to 100%
then another year of cuckato33
then there are four years of cuckatoo34

is this right?

Are there reasons to believe that a memory-IO bound PoW will yield a more competitive mining ecosystem than a compute-bound PoW?

I am concerned that a memory-intensive PoW may actually yield a less competitive mining ecosystem, for a few reasons:

  • There are many possible layouts, architectures, and memory technologies to use in a high-memory ASIC. I think that this flexibility increases the chances of large discrepancies in profitability between mining ASICs. I don’t believe this is the case for PoWs which lend themselves to multiple identical hashing cores, since in that case you just make as fast a core as possible, and stuff as many as you can in the chip.

  • I think that ASIC manufacturers will look to exotic techniques, such as EMIB, in order to overcome inter-die communication latency and bandwidth issues. I think this will increase the design and capital resources needed to create competitive mining hardware, and thus reduce the number of competitive ASICs available.

  • Compute-bound PoW ASICs benefit from packing gates densely on a die, and run them fast and at low power, and dissipate heat. If one ASIC manufacturer is able to obtain a technological breakthrough at one of these things, their compute-bound PoW ASIC will have a huge advantage. However, I think this is unlikely, since these things (gate density, speed, power, and heat dissipation) are highly sought after and researched by foundries and semiconductor companies, being central to profitability and competitive advantage. On the other hand, it’s not clear to me that the architectural concerns of a Cuckatoo Cycle ASIC are as well trodden, so to speak, so I think it more likely that one ASIC manufacturer will find an exotic optimization, perhaps not applicable to other chips, that will reduce the number of competitive ASICs available.

  • Cost of electricity is central to the profitability of compute-bound PoW ASICs. The need to find cheap electricity is actually a decentralizing factor, since cheap electricity is geographically dispersed and not unlimited. If ASICs need cheap electricity to be profitable, then the manufacturer must sell them on the open market, to geographically and politically distributed entities who will be able to mine profitably with them. If cost of electricity is of secondary importance, as may be the case with high-memory ASICs, then the best place to mine with them is as close to possible to wherever they are assembled, and a manufacturer is likely to mine with their own hardware, reducing availability of competitive ASICs.

  • This is a concern specific to Cuckatoo Cycle+, but is worth mentioning since you’ve said that single-die Cuckatoo Cycle ASICs are not meaningfully different from compute-bound PoW ASICs: If smaller graph sizes are periodically made obsolete, in order to prevent single-die ASICs, and older generations of miners are rendered useless, this gives more power to the mining hardware manufacturers, since they do not have to compete against their old chips that they’ve previously sold into the market.

  • In this article you can read about how a new generation of Ethereum ASICs has been released that trounces GPUs and even old ASICs by a huge margin. I think this is more than the difference between subsequent generations of Bitcoin ASICs these days. Unless other companies are able to respond, this may be the only competitive ASIC out there. Although this isn’t directly applicable, but it is an example of an existing high-memory PoW that does not have a particularly competitive mining landscape.

  • Bitcoin ASICs have been around for 5 years, so ASICs for a PoW which is similar to double SHA256 will be easier for existing mining hardware producers to bring to market, which I think would be good for competition.

Unless there strong reasons to believe that a memory-intensive PoW would actually be better than a compute-intensive PoW, I think that such an experiment isn’t worth the risk, because of the above reasons, which I think are reasonable, that it may be worse.

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I believe the current theory is that memory chips have a fairly well defined cost from decades of everyone wanting it small while rearranging logic gates to this months way of edge trimming doesn’t.

Memory chips only have a well defined cost if they’re standard blocks of SRAM or DRAM chips. If they’re custom designs I think that can get quite expensive in terms of IP and design.

On the other hand, I think that rearranging logic gates probably has the most well defined cost, since so much of chip production is just rearranging logic gates.

Right.

Cucatoo32 starts getting phased out after 2 years from launch.
So it’s 2 years of cukatoo34 next.

True; Cuckatoo Cycle is as much about board level optimization as about chip level optimization.

These are challenges that the general computing market is already focussing and competing on (unlike optimizing SHA256 circuitry), so we can expect wider applicability of any optimizations.

As they already do with compute bound ASICs.

We expect cuckatoo miners to be able to handle multiple graph sizes, to get comparable lifetimes to fixed size PoWs.

They have yet to be released, and if the delayed ETH hardfork switches PoW to ProgPoW we may never see then released. In any case, we saw such leap-frogging in earlier bitcoin days as well. It simply takes many years of ASIC development to significantly reduce the size of leaps.

Altogether I admit there are considerable risks to the experiment. At some point I suggested a long term dual pow model with 50% compute bound and 50% memory bound, but this was deemed too complicated.

so cuckatoo32 and cuckatoo33 only get 1 year each?

how much memory is needed to do mean mining for cuckatoo34?