I have comments about ASIC resistance but is this the best place or GitHub?
IMO Lean Miner was never viable for ASIC’s even before the Cuckatoo change. You may be overestimating the SRAM available to a single chip, even at 7nm, but the real killer is power. Even in the Cuckoo formulation, the power requirements of lean miner make it a non-starter.
Right now, mean miner is the only viable published approach, and I would expect to see mean miner based ASICs, making Grin ASIC’s look most like Equihash ASICs: DRAM bound with smallish chip dies produced at 16nm not 7. Most of the chip will be GDDR IO not siphash.
IMO neither PoW is ASIC “friendly”