# Obelisk GRN1 Chip Details **URL:** https://forum.grin.mw/t/obelisk-grn1-chip-details/4571 **Category:** Mining **Created:** [March 20, 2019, 10:02pm UTC](https://forum.grin.mw/t/obelisk-grn1-chip-details/4571 "2019-03-20T22:02:37Z") **Posts on this page:** 1 **Showing post:** 14
### Author: ![Taek](https://avatars.discourse-cdn.com/v4/letter/t/dc4da7/32.png) [@Taek](https://forum.grin.mw/u/Taek) #### Post date: [March 22, 2019, 10:47pm UTC](https://forum.grin.mw/t/obelisk-grn1-chip-details/4571/14 "2019-03-22T22:47:18Z")
> [@asic\_king](#): > > First of all, thanks for sharing. We at Innosilicon also believe that a more open environment will help the ASIC companies gain trust from the blockchain community. In joining this effort, I want to give our view and progress on the development of Innosilicon Grin ASIC. Welcome to the community, and thanks for taking the time to comment! I have long wished that more manufacturers than Obelisk would get involved in the discussion and provide a more transparent view into the world of hardware, so that cryptocurrency communities can make more informed decisions, and also so that the historically adversarial relationship between hardware companies and cryptocurrency communities can become a more collaborative one. > [@asic\_king](#): > > From our first-hand experience in embedding large SRAM we believe going for 512 MiB or over 1 GiB is a dead end. The yield loss will be exponentially higher. TSMC is touting the success of its 7nm process and cites yield of 32MiB (256 Mbit) SRAM at 76%. ([https://www.eetasia.com/news/article/tsmc-unveils-plans-for-7-12-22nm-nodes](https://www.eetasia.com/news/article/tsmc-unveils-plans-for-7-12-22nm-nodes) ) Imagine what kind of yield you will be looking at for 512MiB and beyond. This yield quote is on TSMC’s 7nm process from more than a year before the 7nm process was cleared for mass production. During process bringup yields are usually incredibly low - part of process bringup is improving the yields, and I believe this statistic was chosen to be published because many people thought 7nm was very far away at the time, and yields that good already meant that 7nm was getting very close. Yields today for TSMC’s 7nm process are substantially better. But that’s also not the right comparison point anyway, because Obelisk is using TSMC 16nm, one of the most mature and highest yielding processes in the industry. So not only is it an unfair and misleading statistic to asses 7nm, it’s also unfair an misleading because it’s comparing 7nm statistics to a 16nm chip. Here is a newer article. Though it doesn’t give specific yield statistics, it does mention AI chips that go up to 2 gigabits of SRAM, which is 256 MiB. Clearly, this volume of memory is not as unprecedented as Innosilicon is suggesting. [The New Deep Learning Memory Architectures You Should Know About — eSilicon Technical Article | ChipEstimate.com](https://www.chipestimate.com/The-New-Deep-Learning-Memory-Architectures-You-Should-Know-About/eSilicon/Technical-Article/2018/10/16) > [@asic\_king](#): > > The multi-chips approach minimizes the investment on fixed purpose ASICs and allow the DRAM to be repurposed even after Cuckatoo 32 is phased out. The Bitmain Ethereum miner has DRAMs on it. Those DRAMs cannot be repurposed by a consumer, if you were to repurpose those you would need a professional shop to do it, and you would also need special firmware, and probably a custom board to receive those DRAMs. Bitmain did it this way because it’s cheaper and more efficient to use non-repurposeable DRAM for specialty applications. Doing the repurposing would almost certainly be more expensive than just buying brand new DRAMs - in the case of the Bitmain Ethereum miner, that DRAM is not practically repurposable and nobody is going to try. I had assumed that Innosilicon would be using a similar strategy to save on cost, power, and manufacturing complexity. Innosilicon: are you suggesting instead that your miner will have DRAM that is intended to be repurposed, and if so, how difficult will it be to repurpose and what application / hardware could it be repurposed for? Will consumers be able to repurpose the memory without professional help? > [@asic\_king](#): > > Innosilicon is a strong design company who masters high-speed memory IPs, but there are plenty of IP vendors in this space like Rambus, Synopsys and Cadence that offers similar IPs. Memory interface technology is widely accessible in the industry. It may be widely accessible, but it’s also expensive. Certain manufacturers, namely Innosilicon, have this IP in-house and do not need to pay for it. For everyone else, it is an expense that increases the barrier to entry and makes competition more difficult. This goes against Grin’s goals of having a competitive ASIC ecosystem with many manufacturers. > [@asic\_king](#): > > I wanna highlight the importance of fair play and free market competition for all for anyone who truly want to support the Grin PoW. The Grin core team had formally outlined a very clear goal in its PoW design and a phase-out plan to encourage the multi-chip evolution path using external commodity memories with many months of serious discussion before the final decision for Grin. Whoever wants to supply the Grin mining equipment should adhere closely to the announced PoW rules instead of attempting to tailor the PoW for one’s self interest. Whether using multi-chip strategy or single chips is vendor’s own technical choice. Afterall, you make the chip to support Grin, not the other way around. Obelisk’s current roadmap includes both a CC31 miner in October, and a single-die CC32 miner in April. Similar to the performance difference between the Antminer S7 and the Antminer S9 (both TSMC 16nm products), we expect computational speed and efficiency to roughly double. Because CC32 is more computationally complex, these things cancel out. Our internal target for our CC32 miner is 200 graphs per second at 1000 watts. The phase out creates a planned obsolescence for our customers buying the GRN1, and that harms the value of the GRN1. However, we believe that the total block reward for AF-CC31 still makes sense to move forward with production, provided that we are careful with total production volumes. At the current price for Grin, we would probably ramp back a bit from the originally planned 10,000 units, though we have not yet fully determined what is appropriate. It’s also difficult for us to determine production volumes when our competitor - who claims to have an earlier shipping date (summer vs. fall) - has not yet released an indication of what the specs are or how many machines they intend to produce. Obelisk currently believes that we will be able to capture the CC31 and CC32 markets both regardless of the phase-out, however that requires charging our customers more than twice as much for NRE over the next 18 months. CC32 also requires moving away from 16nm in order to avoid TMTO, which means tape-out costs will be higher and barrier to entry will be more difficult for competitors. This is actually good for Obelisk, as it means less competition and higher margins, but I don’t think it’s good for the Grin network. The original goal of the phase-out was to ensure that single-die ASICs could not be created for the Cuckatoo algorithm. I had protested this at the time, though because I didn’t have strong yield statistics and we hadn’t done the full work on analysis yet, I was unable to confidently assert that single-die ASICs would be viable at Cuckatoo31 and beyond. Obelisk has since shown this, and we are confident asserting that we do not believe multi-die ASICs will be competitive at any Cuckatoo before Cuckatoo35 thanks to the sheer amount of memory you can fit on a single die, and thanks to the fact that yields are in fact not as bad as many fear. For those still doubting that Obelisk’s chip is viable, I have included a link to a third-party audit of our chip that we had done, both to assure ourselves that we were not making a mis-step, and to assure others that we are a world-class team that is staying within the limits of the technology that we are working with even when we are pushing the boundaries of what people thought was possible: [https://pixeldrain.com/l/o3hi6WtF#item=0](https://pixeldrain.com/l/o3hi6WtF#item=0) > [@tromp](#): > > The goal of the commitment was to protect large CC ASIC investments. I believe that such investments have already been made for C32, based on our planned phase out of C31. In which case we shouldn’t undo the latter. I fully agree that Grin needs to protect large CC ASIC investments, and that changing the promise creates uncertainty and harms manufacturer willingness to participate. However, it is not clear to me that delaying the phase-out of Cuckatoo31 is actually damaging to anyone. Cuckatoo32 miners are already allowed on the Grin network today, and in fact get to mine at an advantage. That is, from a per-edge basis, Cuckatoo32 solutions have more weight than Cuckatoo31 miners. Because this bonus weight exists, the primary advantage of the phase-out of Cuckatoo31 to another manufacturer is that competition is eliminated. And that as the sole advantage goes against the stated goals of the Grin ASIC-friendly PoW algorithm - to foster competition between ASIC manufacturers. The phase-out, to the best of my knowledge, does not exist to make miners obsolete, but instead to prevent single-die ASICs from entering the marketplace. But as Obelisk has discovered, Cuckatoo32 and Cuckatoo33 are both feasible to do without a 2x TMTO on a single-die chip using today’s technologies. Even where big investments have been made, I believe that the primary effect of eliminating the phase-out will be increasing competition overall. I believe, based on several conversations I’ve had with people looking to buy Grin miners, Bitmain, Whatsminer, and Canaan all considered making a Grin ASIC, and all decided against it, with the primary reason being the fractured block reward. With the block reward being spread over 3 different algorithms (Cuckaroo29, Cuckatoo31, Cuckatoo32) over the typical expected lifetime of a miner, the incentive for manufacturers to enter is substantially reduced. I believe that it would help the discussion a lot if Innosilicon published more information about their miner. As of now, we don’t even know the full range of algorithms that it is capable of targeting. Innosilicon continues to claim that they will be able to ship by the end of the summer. In order for that to be possible, Innosilicon will need to have finalized their architecture already and be working on implementation. So these questions at this point in time should all be reasonable: - Is the miner a mean miner or a lean miner? - Does the chip itself have a significant amount of memory on it? - Is the miner capable of targeting Cuckaroo29 in addition to Cuckatoo31 and Cuckatoo32? - How many graphs per second are you expecting (+/- 25%) on Cuckatoo31? Cuckatoo32? Cuckaroo29? And what ballpark (+/- 50%) are you expecting for power consumption? > [@asic\_king](#): > > We will demonstrate to the world that the multi-chip ASIC solution will work better It does not seem like Innosilicon is concerned about Obelisk’s single chip designs. Based on their own confidence, it does not seem like they believe nixing the phase-out would change the dynamics between Obelisk and Innosilicon, and as best I can tell there is no other ASIC manufacturer seriously considering Grin at this time. --- _[View the full topic](https://forum.grin.mw/t/obelisk-grn1-chip-details/4571)._