I’m ensuring that there are pins in the first place. I.e. that you cannot build a single chip ASIC. This is discussed at length in https://forum.grin.mw/t/scheduled-pow-upgrades-proposal
No; you can just increment PART_BITS which doubles the number of passes you make over remaining edges in each round. See
You will however need to provide enough DRAM to store the bigger edge bitmap. Which is similar to ethash miners having to account for an eventual doubling of DAG size.