# Advice on Cuckatoo hardware implementation

**URL:** <https://forum.grin.mw/t/advice-on-cuckatoo-hardware-implementation/12042>\
**Category:** Development and Technical Discussion\
**Created:** [August 23, 2025, 11:40pm UTC](https://forum.grin.mw/t/advice-on-cuckatoo-hardware-implementation/12042 "2025-08-23T23:40:09Z")\
**Posts on this page:** 1\
**Showing post:** 4

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**Author:** ![tromp](https://yyz2.discourse-cdn.com/flex036/user_avatar/forum.grin.mw/tromp/32/22_2.png) [@tromp](https://forum.grin.mw/u/tromp)\
**Post date:** [August 24, 2025, 7:20pm UTC](https://forum.grin.mw/t/advice-on-cuckatoo-hardware-implementation/12042/4 "2025-08-24T19:20:57Z")

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> [@CouchStudyAttire](#):
>
> Grin now operates on Cuckatoo32 only

Correct; since the final pre-planned Jan 2021 hardfork.

> [@CouchStudyAttire](#):
>
> -ePic jammed 512mB of SRAM into a single die, project did not ship.

Taek from Obelisk announced the Cuckatoo31 GRN1 ASIC at [https://forum.grin.mw/t/obelisk-grn1-chip-details/](https://forum.grin.mw/t/obelisk-grn1-chip-details/) , while Henry Quan from ePIC gave a talk about it at GrinCon1: [https://www.youtube.com/watch?v=n01GnIn2Hs0&list=PLvgCPbagiHgrQa5KVt4XixK9t\_NbfpkuP](https://www.youtube.com/watch?v=n01GnIn2Hs0&list=PLvgCPbagiHgrQa5KVt4XixK9t_NbfpkuP)

> [@CouchStudyAttire](#):
>
> (Im guessing this is the chip in Ipollo miner?)

I don’t think so. ASAIK the Ipollo ASIC is not multi-chip.

> [@CouchStudyAttire](#):
>
> C32 is essentially proof of 512mb SRAM

I meant that the most efficient implementation, minimizing Joules/graph, would need to use that much SRAM. It would need an additional 512MB of serially accessed memory for the edge bitmap, which could be external DRAM.

> [@CouchStudyAttire](#):
>
> I’ve read that DRAM has too much latency

DRAM indeed has way too much latency for the purely random access to node bits, while also wasting too much energy, since only one bit out of a whole cache-line is needed. Thus, DRAM is only useful in mean mining as used on GPUs.

> [@CouchStudyAttire](#):
>
> perhaps a FPGA to be able to optimize the memory accesses

FPGAs are quite unsuitable for C32 lean mining, having very limited on-chip SRAM and limited bandwidth to external SRAM chips, which also happen to cost a fortune.

> [@CouchStudyAttire](#):
>
> I’m trying to make a homemade Grin miner, mostly from off-the-shelf components, avoiding custom silicon($$$) if possible.

Avoiding ASICs means that lean mining is ruled out, and for mean mining, existing high end GPUs are probably already close to optimal, as your performance mostly depends on memory bandwidth.

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